Three dimensional (3D) integrated circuits (ICs) have been employed to increase functionality in a small footprint. For example, a 3D IC is formed by stacking dies and interconnecting them vertically so that they behave as a single device. The stack dies are interconnected by using through silicon via (TSV) technology. TSV technology includes forming TSV contacts, such as copper contacts, which extend though the surfaces of the wafers or dies. The use of TSV contacts can shorten electrical paths, leading to faster operation.
However, there have been problems encountered in conventional TSV processing. For example, to increase performance and reduce cost, larger and thinner wafers are used in semiconductor processing. Thinner and larger wafers are prone to warping. This may lead to problems during processing, such as chemical mechanical polishing (CMP). For example, wafer warpage makes it difficult to control layer uniformity during CMP. Other issues of conventional TSV processing include outgassing during copper barrier formation.
From the foregoing discussion, there is a desire to improve TSV technology to facilitate 3D ICs.